A significant number of integrated circuits are fabricated utilizing CMOS circuitry due to the low power consumption of CMOS devices, particularly in the quiescent (non-switching) state. Testing a CMOS device quiescent power supply current (IDDQ) is a useful technique because excessively high IDDQ current may indicate a defect in the circuit that may result in premature failure of the circuit. An excessive IDDQ current might be caused by, for example, gate oxide leakage within the device indicating a poorly fabricated integrated circuit. Moreover, it has been determined that CMOS devices having high IDDQ may, although functional at the time of test, be unreliable and thus exhibit a shorter than desirable operating lifetime.
Integrated circuits, including CMOS integrated circuits, are typically extensively tested prior to shipment to a customer and installation in a multi-component electronic system. Given the large size of CMOS integrated circuits, the testing is extensive and is performed by sophisticated electronic test systems, such as the Polaris tester available from Mega Test Corporation of San Jose, Calif., the assignee of this invention.
A typical semiconductor test system depicted in FIG. 1 includes a test controller 101 which provides digital signals to control the operation of timing generators 102, a device under test (DUT) power supply 103, and DC measurement system 104 of the semiconductor test system. Subsections 102, 103, 104 are connected to test head pin electronics 105 which transmits highly accurate test signals to DUT 106 and monitors the pins of DUT 106 in order to measure voltages, currents and logic levels. In this manner, DUT 106 is tested for proper functionality under a wide range of operating conditions. The DUT power supply 103 of the semiconductor test system is programmable to provide desired voltage and current levels. The DC measurement system 104 is also programmable to provide appropriate current and voltage measurement ranges. One difficulty in such prior art test systems is that current measurement ranges vary considerably between high current ranges used to measure operational current IDD, such as output buffer current capacities, and the extremely low current ranges used to measure quiescent current IDDQ.
FIG. 2 is a block diagram depicting a typical prior art power supply 103 useful in measuring both high and low current ranges thereby suitable for use in measuring both IDD and IDDQ of a CMOS integrated circuit. As shown in FIG. 2, busses 201, 202 are used to communicate between the test controller/pattern processor 101 and digital interface/sequencing circuit 203. A voltage reference VREF is received on input terminal 205 and applied to power amplifier 207 to provide a buffered reference voltage output BUFOUT. This buffered output voltage is applied to a parallel array of current range analog switches 208, 209, 210, which are each coupled to current sense resistors 211, 212, and 213, respectively. The resistors are then coupled to VDUT output terminal 218 which provides a desired voltage to DUT 106. VDUT terminal 218 is also coupled to current sense multiplexer 215 which serves to monitor the voltage across, and thus the current through, current sense resistors 211, 212, and 213. A current sense signal is output from current sense multiplexer 215 and applied to comparison circuitry 204 to compare the current sense signal against a predetermined threshold. Comparison circuit 204 communicates with digital interface/sequencing circuit 203 in order to validate the current levels as acceptable, or to set an error flag when the current level is beyond the threshold. Current clamp 206 serves to control power amplifier 207 in response to the current sense output of current sense multiplexer 215 in order to prevent damaging the integrated circuit and the current sensor 204.
Buffer 214 receives a sense signal from the DUT voltage supply pins in order to correct for voltage losses in the force line at VDUT terminal 218. Buffer 214 also buffers the supply from a feedback resistor 217 to power amplifier 207. This type of connection is known in the art as a Kelvin Connection.
During the operation of prior art circuit of FIG. 2, the integrated circuit is tested according to the flow chart of FIG. 3. In step 302, the power supply 103 is programmed to a high current range by closing switch 210, which is associated with a low value resistor 213. Then, in step 304, a test vector is executed to bring DUT 106 to a known state. A high current range resistor (low impedance value) is used during this period since DUT 106 is being exercised causing the internal transistors to turn on and off and thus utilize an operational supply current IDD. Ordinarily, various performance parameters of DUT 106 are measured during operational testing.
Once a desired state is achieved, also known as a test vector, the exercise is stopped, causing the device under test to cease switching its internal transistors. Step 306 closes switch 208 and the device under test power supply 102 is set to a low range, the IDDQ current range. In step 308, switch 210 is opened. A transient is created at the VDUT terminal when the switch 210 is opened due to accumulated charge in the switch. After the IDD current settles, in step 310, the quiescent current IDDQ is measured across resistor 211 by current sense multiplexer 215. If, as determined by comparison circuit 204, the measured IDDQ current is beyond the threshold, an indication signal is sent to digital interface 203 and appropriate action taken, for example by notifying the test engineer, or indicating that the part failed the IDDQ test.
Next, in steps 312 and 314, DUT power supply closes switch 210 and opens switch 208, and returns the procedure to step 304 where the power supply 103 is programmed back to a high current state. This switching causes another transient in the VDUT signal because of the impedance mismatch between the sensing resistors. Once the VDUT signal settles, testing is repeated with a different test vector established by the test controller 101 to test IDDQ based on different internal states so that a wide variety of defects can be detected.
As discussed briefly above, switching among the various sensing resistors causes transients to appear at the VDUT terminal. The prior art DUT power supply design (FIG. 2) which has IDDQ measurement capability causes transients in VDUT when a high impedance sense resistor 211 is switched out and a low impedance sense resistor 213 is switched in, and node voltages BUFOUT and VDUT are different. The difference between these voltages, before the switch is made, is equal to the IDDQ current times the IDDQ current sense resistor 211. When switch 208 is opened and switch 210 is closed, the current into VDUT terminal 218 becomes the difference between nodes BUFOUT and VDUT divided by the high current sense resistor 213. Since current sense resistor 213 is a much lower impedance than current sense resistor 211 and since BUFOUT is greater than VDUT at the switch time, the resulting current is large. This high current will continue until power amplifier 207 corrects BUFOUT to the appropriate level to maintain the VDUT voltage at the programmed level. Because a time delay is associated with the feedback loop to control the power amplifier, the surge of current will cause a voltage variation at VDUT terminal 218.
FIG. 4 shows a timing diagram depicting the operation of the prior art circuit of FIG. 2. When a transition is made during step 308 when switch 210 is opened, a transient is created at the VDUT terminal due to the accumulation of charge. Moreover, when a transition is made during steps 312 to 314, a transient is created at the VDUT terminal due to the mismatch in driving impedance.
The difference between the BUFOUT and VDUT voltage levels within the power supply 103 is the voltage appearing across the selected current sense resistor, with IDDQ being defined by EQU IDDQ=(BUFOUT-VDUT)/RIDDQ,
where IDDQ is the resistance value of the selection current sense resistor. When the transition is made from step 312 to step 314, a lower value resistor 213 is placed in series with the CMOS integrated circuit. This lower value resistor 213 allows the VDUT voltage to increase because the power amplifier 207 (BUFOUT) had previously been driving a large value resistor 211, and consequently there was previously a large difference between the voltages BUFOUT and VDUT.
Moreover, as shown in FIG. 4, if current range switching is performed with solid state switches, a charge (ICHG) is injected into the system, causing a transient increase in the voltage level of VDUT. As a result, test time must be increased in order to allow his transient effect on VDUT to be discharged before a measurement is made. Increased test times increase the cost of test since fewer devices can be tested in a given amount of time on a given tester. While relays can be used rather than solid state switches as switches 208 through 210, charge injection will be much smaller but switching times will be much longer, also resulting in long test times. However, the life expectancy and reliability of relays is significantly less than that of solid state switches. Furthermore, under some conditions, noise will be injected into the DUT supply voltage when switching from an IDDQ measurement range to a higher current range. This noise makes the IDDQ test less reliable or requires a significant additional time for the IDDQ test since measurements cannot be made until the noise transients have dissipated.